This invention relates to address-counter control systems used for refresh operations required for volatile memories, such as DRAMs (dynamic random access memories), having ECC (error checking and correcting) circuits. More particularly, this invention relates to an address-counter control system which has a simple structure and can be readily controlled.
To explain a known-type of address-counter control system, an ECC circuit and a refresh operation of a volatile memory will first be described.
In general, to avoid a loss of memory data due to aging, a volatile memory, such as a DRAM, executes a refresh operation for periodically reading memory data, amplifying it through a sense amplifier, and writing the amplified data back into the memory, as explained in Japanese Unexamined Patent Publication No. 56-98781 (see FIGS. 1 and 3 in the publication), which will be hereinafter referred to as a first document.
First, description will be made of an example of a refresh operation for a memory 10 with reference to FIG. 1. For a refresh operation, in the memory 10, a row-address signal for a refresh address is input via a row-decoder 11 to sequentially scan all the rows in a memory array 12 in an X direction, which is a column direction, without the use of a column decoder 13. Thus, all data bits in a Y direction, which is a row direction, are read for each row and are amplified by a sense amplifier 14, and the amplified data bits are written into the original memory elements to thereby prevent degradation of the memory bits.
The refresh address is internally and automatically created. That is, a ring oscillator, constituted by an oscillator circuit in which an odd number of inverters are connected in a ring, generates clock signals, and a refresh counter counts the clock signals to thereby sequentially generate the refresh address.
This refresh operation uses, for example, an ECC circuit for detecting error bits and for writing corrected data into the original memory elements using a known method, as described in the first document (see FIG. 3 thereof). This is adapted to repair memory elements crashed by radiation or the like.
Referring to FIG. 2, a refresh counter 26 sequentially activates an address register 27 for refreshing to control an address selector 25, thereby driving a row decoder.
An ECC circuit for the memory 10 will now be described with reference to FIG. 2. The memory 10 includes a normal region for data bits and a parity region for storing check bits (parity bits) for detecting an error. When write data is input into the memory 10 via a data selector 21, a check bit generator 22 monitors the data bits being input and generates check bits corresponding to the predetermined numbers of data bits. The generated check bits are written into predetermined locations, which correspond to the locations of the associated data bits, in the parity region in the memory 10.
During a refresh operation, an error detection and correction section 23 compares data bits read from the normal region in the memory 10 with check bits corresponding thereto read from the parity region. Upon detecting error bits, the error detection and correction section 23 locates the position thereof, inverts the bits, and sends the resulting bits, as error-corrected data, to the data selector 21, so that the data is written into the memory 10.
The refresh operation is executed for all the memory elements in the normal region and the parity region in the memory 10.
For example, when the memory cells shown in FIG. 1 have an “m×n” matrix structure, upon reading or refreshing, a decoder 11 decodes a row address in the memory array 12 so that one-row line therein is selected. In this case, data of “n”-bit corresponding to the number of the columns is passed in parallel through the sense amplifier 14 and is amplified thereby.
For a normal reading operation, since the column decoder 13 decodes a column address and the column selector 15 selects one column line in the memory array 12, one of “n” bits is sent as read data to the outside.
For a refresh operation, reproduced data amplified by the sense amplifier 14 is returned to all the column lines in the memory array 12 and is written into the memory cells in a column line selected at this point.
The address configuration in a memory bank 120 constituted by the memory array 12 will now be described with reference to FIGS. 3 and 4. For example, in a 256-megabit address region, a normal address region (hereinafter referred to as a “normal region”) in which data bits are stored uses row-addresses “x0 to x12”. Of these addresses, four row addresses “x9 to x12” are used to divide one bank into 16 memory mats (hereafter referred to as “mats”) 0 to 15 and nine row addresses “x0 to x8” are used to divide each mat into 512 subwords.
Meanwhile, arranging a parity address region (hereinafter simply referred to as a “parity region”) for check bits in each mat minimizes a disadvantageous use of memory area. Thus, four addresses, i.e., row addresses “x9 to x12” are used to specify corresponding 16 mats in one bank, and an address of a row-address “x13” is used to specify partitioning between the normal region and the parity region. Four row addresses “x0 to x3” are sufficient since 16 parity address regions are provided for 512 subwords.
As a result, It is required that the refresh counter corresponds to the column addresses “x0 to x12” in the normal region and to the row addresses “x0 to x3” and “x9 to x13” in the parity region.
As described above, the normal region and the parity region are in an irregular relationship. A counter circuit for refreshing, however, is not disclosed in the first document. Referring to FIGS. 5A, 5B, and 5C, for a typical refresh counter, two counter circuits, i.e., a normal-region address counter circuit shown in FIG. 5A and a parity-region address counter circuit shown in FIG. 5B are prepared. Thus, the counter circuit shown in FIG. 5A continuously counts contiguous addresses of normal-region address counters (NACs) 102-0 to 102-12 and the counter circuit shown in FIG. 5B continuously counts contiguous addresses of parity-region address counters (PACs) 103-0 to 103-3 and 103-9 to 103-13.
For a long-term refresh operation, a general counter circuit shown in FIG. 5C counts “N+1” addresses until the refresh operation for all the bits is completed.
Upon a long-term refresh operation, after refreshing the normal region, the refresh counter circuit refreshes the parity region. After completing the refreshing operation for all the regions, among internal power supplies, a power supply for a circuit that does not affect the data retaining operation is shut off for a certain period of time until the next refresh operation, to reduce power consumption.
This pause period will now be described with reference to FIG. 6. Herein, it is to be noted that FIG. 6 makes reference to FIG. 34 of Japanese Unexamined Patent Publication No. 2002-56671 which will be hereinafter referred to as a second document.
In the illustrated example, a primary oscillator OSC defines the cycle of a refresh operation. After a pulse in the oscillator OSC rises and a specified time TPON elapses, an internal power supply rises. In response to the rise of the internal power supply, intensive refreshing is executed on all the bits in the memory. Upon completion of this refresh operation, the internal power supply is put into a pause state. This pause state continues, until another refresh cycle arrives and the next pulse rises in the primary oscillator OSC. Thus, to detect the completion of the refresh operation, the general counter circuit shown in FIG. 5C includes N+1 general counters (CNTs) 104-0 to 104-N.
Although neither of the first document nor the second document discloses a counter circuit for refreshing, a refresh counter typically requires three counter circuits, as described above.
The known address counter control circuit described above has a problem in that the area of a memory device must be disadvantageously reduced.
The reason will be as follows. Namely, the known address control circuit includes a counter for a normal region with contiguous addresses and a counter for a parity region with non-contiguous addresses and further includes a counter for detecting the completion of an entire refresh operation.